As a semiconductor device capable of suppressing generation of parasitic capacitance, a semiconductor device using a Sol substrate is currently used. The SOI substrate is a substrate obtained by forming a BOX (Buried Oxide) film (embedded oxide film) on a supporting substrate made of high-resistance Si (silicon) or others and forming a thin layer (silicon layer) mainly containing Si (silicon) on the BOX film. When a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: MOS field-effect transistor) is formed on the SOI substrate, the parasitic capacitance generated in a diffusion region formed in the silicon layer can be reduced. Therefore, by manufacturing a semiconductor device by using the SOI substrate, improvement in an integration density and an operating speed of the semiconductor device, achievement of latch-up free, etc. can be expected.
Patent Document 1 (Japanese Patent Application Laid-Open Publication No. 2009-158677) describes a technique that a nitride film for a dummy sidewall is formed on a side wall of a gate electrode on a SOI substrate via an oxide film for a sidewall, and then, a selective epitaxial growth region is formed on a SOI layer of an upper surface of the SOI substrate, followed by removal of the nitride film for the dummy sidewall, and then, implantation of an impurity for extension and an impurity for halo into the supporting substrate. Here, the document does not specifically describe at which position in the supporting substrate a Halo portion (halo region) formed in the supporting substrate is formed, and does not describe how different a concentration of the impurity configuring the Halo portion is between a portion right below the gate electrode and other regions, either.
Patent Document 2 (Japanese Patent Application Laid-Open Publication No. 2007-188992) describes a technique that, when a MOSFET is formed on the SOI substrate, a high-concentration diffusion region is formed in a vicinity of a surface of the supporting substrate right below the gate electrode, the high-concentration diffusion region being formed in regions which are below a drain region and below a source region and at a predetermined depth from the surface of the supporting substrate.
Patent Document 3 (Japanese Patent Application Laid-Open Publication No. 2010-251344) describes a technique that a p-well is formed in the entire upper surface of a silicon substrate below the SOI substrate, and an n-channel-type MIS transistor is formed on the SOI layer thereon.